Light emitting diodes (LEDs) have been tremendously successful in the last decade, both in replacing traditional light sources in most lighting applications and enabling new products related to signaling, visualization and illumination. This success story was accompanied by a significant technological evolution of LED devices, making them significantly more complex. Besides this, upcoming challenges like integration of LEDs and ICs on chip level and the development of micro-LEDs will pose new challenges for materials and processes required for LED manufacturing.

Atomic layer deposition (ALD) technique has traditionally been used for controlled deposition of high-quality thin films for the semiconductor industry. Furthermore, its capability to deposit a wide range of materials as conformal and pinhole-free films on challenging substrates and topographies makes it a valuable tool for LED makers to tackle the challenges ahead.

Used in LED devices, ALD films can serve or contribute to electrical and chemical passivation layers, reflective or anti-reflective coatings and moisture barriers for example. Choosing the right combination of materials and processes for each application based on existing literature is not easy since most studies focus either on a specific material or specific materials properties.

In this work we have done a material screening of several ALD oxides, including varying oxygen source (H₂O/O₃) and deposition temperature (100°C-300°C depending on material) to find the best solutions for LED applications. The selected materials included Al₂O₃, Ta₂O₅, SiO₂, Nb₂O₅, TiO₂, HfO₂, ZrO₂, and Y₂O₃. The PICOSUN^® 200 Advanced ALD reactor was used for the depositions.

Electrical, optical, morphological and chemical properties of the films were studied. For comparison of water vapor transmission rates (WVTRs) in a realistic setup, a specific capacitive sensor developed by OSRAM [1] was employed.

This sensor device basically consists of a hygroscopic sensor dielectric placed between metal electrodes. The top electrode is perforated to enable moisture penetration into the sensor dielectric. The whole device is encapsulated with the moisture barrier material under test. In a controlled hot and humid environment, water molecules penetrating though the barrier layer are absorbed in the sensor dielectric and increase the capacity of the sensor. From the rate of capacity increase, the WVTR of the barrier layer can be derived.

[1] A. Rückerl et. al. Microelectronics Reliability 54(9-10) 2014

High specific surface powders in polymeric or inorganic matrices requires a fine control of their properties. The design of these nanoscopic agents is linked to the development of nanotechnology processes which can be transferred from planar substrates to complex 3D surfaces. In this framework we showed how self-limiting reactions inspired by Atomic Layer Deposition can be applied to functionalize powder by using a specifically designed Fluidized Bed Reactor. A specific interest has been given to work in non-saturated regime with nickel or Cobalt acetylacetonate to obtain well controlled metal nanocatalysts of 5-10nm diameter. Depending on the process window, some interesting properties have been demonstrated such as ferromagnetic behavior or the systematic recover of the Metal-Carbide phase that increase the throughput of Carbon Nanotubes growth. These activated nanostructures can expressly improve the electrical, the thermal or the mechanical properties of some related composites depending on how some processing parameters such as exposure time, pressure or local temperature can be tailored.

The development of the conformal thin film process is at high importance, especially in 3D memory applications. High aspect ratio structures, new materials, and demanding geometries are challenges for the tool manufacturers, material developers, and in inspection and testing. PillarHall® Lateral High Aspect Ratio (LHAR) silicon test chip has proven its value in conformality metrology and elemental mapping of the trench wall [1-5] where single chip on the center of a carrier has been a typical approach. Here, we examined the PillarHall® test chip compatibility to wafer level conformality mapping using specially designed PillarHall® LHAR4 small chips, on a 150-mm wafer scale with a silicon-based chip holder to enable attachment of multiple chips on a selected wafer locations. Studied process was Al₂O₃ made by ALD at 300 °C using 500 cycles in Picosun R-150 ALD reactor with variable pulse-purge sequences. Chips were stabilized in the process chamber for 30 minutes at ALD temperature, before the process was started.The film thickness was measured with spectroscopic reflectometry SCI FilmTek 2000M using 49 pts and 100 pts measurement for full wafer and for the LHAR4 chip, respectively. The film thickness on planar surface, 150-mm wafer was 47.3±0.2 nm which was in-line with the film thicknesses measured from opening of the LHAR4 chips, varying from 45.8 to 48.3 nm. The half thickness penetration depth, PD^50% varied a from 184 to 232. The reason and repeatability for the variation in the PD^50% across the 150-mm wafer are still unconfirmed and can be e.g. due to small gradients in temperature and pressure, and precursor flow designs in the reactor system. Although reasons of conformality variations at wafer level are not well-known, PillarHall® provides information of the minimum reachable aspect ratio. This information can be used to develop experimentally process parameters for specific aspect ratio requirements for the full wafer area. Furthermore,the presented platform enables easy and fast methodology to improve understanding of the factors influencing on the wafer level conformality.

[1] F. Gao, S. Arpiainen, R. L. Puurunen, J. Vac. Sci. Technol. A 33 (2015) 010601. http://dx.doi.org/10.1116/1.4903941.

[2] M. Ylilammi, O. M. E. Ylivaara, R. L. Puurunen, J. Appl. Phys., 123, 205301 (2018). https://doi.org/10.1063/1.5028178.

[3] K. Arts et al., J. Phys. Chem. C 123 (2019), 44, 27030-27035, https://pubs.acs.org/doi/10.1021/acs.jpcc.9b08176

[4] K. Arts et al., J. Vac. Sci. Technol. A, 37 (2019). https://doi.org/10.1116/1.5093620

[5] A. M. Kia et al., Nanomaterials 9 (2019). https://doi.org/10.3390/nano9071035.

Cuprous oxide (Cu₂O) is a non-toxic and abundant p-type semiconductor with a direct band gap around 2.1 eV and a large visible absorption coefficient. It has been studied and developed for several devices such as solar cells, thin film transistors or batteries. In this study, an innovative technique for depositing conformal and high-quality thin films, AP-SALD (Atmospheric Pressure Spatial Atomic Layer Deposition), is used to deposit Cu₂O at low temperatures (up to 260 °C), under atmospheric pressure for photovoltaic applications. AP-SALD is an alternative approach to conventional ALD in which the precursors are separated in space rather than in time, allowing fast deposition rates as compared to conventional ALD (up to nm/s in some cases).

The aim is to optimize the low-cost Cu₂O deposition by AP-SALD on different substrates, even flexible, with a control over growth rate and transport properties (mobility and concentration of carriers). The effect of deposition parameters has been carefully studied, and mobility values of 91 cm²V^-1s^-1 have been obtained, close to values associated to epitaxial Cu₂O thin films or Cu₂O single crystals. Optimized Cu₂O thin films, combined with n-type ZnO also deposited by AP-SALD, lead to all-oxide solar harvesters with efficiency rivaling values for similar devices made with high temperature and/or vacuum approaches. This shows that AP-SALD is a suitable approach to fabricate all-oxide solar harvesters, on both glass and flexible substrates.