ALD/ALE 2026 Session AA-TuP: ALD Applications Poster Session

Atomic layer deposition (ALD) provides atomic-scale thickness control and excellent conformality, enabling the integration of thermoelectric materials onto complex, high–aspect ratio architectures. In this study, Sb₂Te₃ thin films were deposited by ALD on planar and porous silicon substrates and subsequently modified through ion implantation to independently tune electrical and thermal transport. Chromium (Cr⁺) and argon (Ar⁺) ions were employed to decouple chemical doping from structural disorders. Cr⁺ implantation was used to adjust carrier concentration through electrically active doping, while Ar⁺ implantation introduced lattice defects and disorder without chemical substitution. Post-implantation annealing at 225 °C enabled partial defect recovery and dopant activation. Hall effect measurements reveal a substantial increase in carrier concentration and electrical conductivity in annealed, implanted films compared to pristine as-deposited samples. This enhancement is accompanied by reduced carrier mobility, consistent with increased carrier scattering from implantation-induced defects. These results demonstrate that combining ALD-enabled conformal growth with controlled ion-beam defect engineering offers a scalable pathway for optimizing Sb₂Te₃ thermoelectric thin films through independent control of electronic and phononic transport.

Extreme Ultraviolet Lithography (EUVL) has become essential process for reduction in device dimension. Recently, in EUVL, Dry-deposition & Dry-development approaches have attracted considerable attention because of their capability of preventing pattern collapse, relaxing Resolution-Line edge roughness-Sensitivity (RLS) trade-off, and reducing environment effect. As Photoresists (PR) for Dry EUVL, Sn-based precursors with EUV-sensitive ligands have been widely researched due to high absorption coefficient of Sn towards EUV light.

In this study, we developed a new Sn precursor as a dry PR for EUVL. The thin PR films of 25 nm were deposited through chemical vapor deposition (CVD). Then, 5X5 μm² patterns and 1:1 line/space (L/S) patterns were formed through E-beam lithography process for measurement of sensitivity resolution and line-edge roughness (LER) of the developed dry PR.

The sensitivity of the dry PR was evaluated with E-beam dose when thickness after development reaches maximum with increasing the dose for 5X5 μm² patterns. The thickness of those patterns after development were measured through optical microscopy. D₁₀₀ (Dose at maximum thickness) of the PR was 399 μC/cm² at the voltage of 100 kV.

1:1 L/S patterns with half pitch = 50, 40, 30, 20, and 10 nm were observed with scanning electron microscopy (SEM). From hp = 50 nm to hp = 20 nm, no major defects (pattern collapse, bridging and line pinching) was observed. LER at hp =20 nm measured with Lacern program was only 1.66 nm. These results showed that our developed dry PR has satisfactory performances to realize ultra-fine nano-patterns for reducing dimension of semiconductor devices.

Metal halide precursors are widely used in Atomic Layer Deposition (ALD) and Chemical Vapor Deposition (CVD) due to their high reactivity with common oxygen sources and exceptional thermal stability. These characteristics enable excellent conformality and often produce high-purity films with lower carbon and oxygen contamination compared to many organometallic precursors. However, despite their effectiveness, a notable limitation is that most metal halides exist in the solid phase, which complicates precursor delivery and necessitates the use of specialized canisters. Additionally, corrosive reaction byproducts (e.g., HF, HCl) can damage ALD chamber components. To address these limitations, we developed a novel niobium (Nb) precursor by combining halide and organic ligands. This new Nb precursor synergizes the advantages of both ligand types; it retains the reactivity of halides while exhibiting exceptional air stability and existing in the liquid phase at room temperature. Notably, the precursor demonstrated excellent properties during the deposition process. Its liquid state facilitates stable delivery, and its superior thermal stability allows for deposition at higher temperatures. Consequently, the precursor was confirmed to achieve perfect step coverage (~100%) on patterned wafers, comparable to that of conventional metal halide precursors. We expect this new Nb precursor to be a suitable candidate for the ALD of Nb2O5 interfacial oxide layers.

Hydrogen sensors are crucial devices for securing hydrogen based power generation systems. As the conventional technologies, palladium nanoparticle films were used as measuring its resistance as the H₂ signal. Moreover, the transparent oxide semiconductors such as ZnO were used as the sensing resistor for hydrogen. On the other hand, thin–film–transistor (TFT)–based sensors are attracting increasing attention because a TFT matrix can be used as a two–dimensional sensing platform. In the present study, ZnO–based TFT sensors were fabricated by atomic layer deposition to explore their potential for hydrogen detection.

In Fig. 1, the schematic of the TFT is illustrated. A nanometer–thick (12 nm) ZnO film was used as the channel layer, and the thickness was minimized to enhance the sensitivity. The ZnO film was deposited by room–temperature atomic layer deposition. The deposition system is shown in Fig. 2. The precursors were dimethylzinc and plasma–excited humidified argon. The deposition temperature was room temperature. The film was then annealed in dry air at 450°C for 30min to promote crystallization. In this TFT, the channel length and width were 60μm and 1mm, respectively.

For the hydrogen sensing test, we measured the time variation of the drain current with gate and drain voltages of 0 and 20V, respectively. The hydrogen partial pressure was increased stepwise from 200 to 6400Pa. The drain current clearly increased with increasing partial pressure, although no saturation was observed. It was also confirmed that the slope of the drain–current response correlated with the partial pressure, suggesting the applicability of the present device as a hydrogen sensor. We assume that hydrogen molecules were adsorbed on the palladium oxide, dissociated into atomic hydrogen, and diffused into the ZnO channel, where the enhanced carrier conduction led to the steep increase in drain current.

Proton-exchange membrane (PEM) water electrolysis is a leading technology for green hydrogen production, offering high efficiency and compact design. However, its widespread adoption is hindered by the reliance on costly platinum group metals and titanium-based components required to endure the acidic, oxidizing environment during operation [1].

Titanium-based components, such as the porous transport layer (PTL) and bipolar plates, play critical roles in facilitating mass transport, ensuring uniform current and heat distribution, and providing mechanical stability to the system. Yet, under operational conditions, these components form semiconducting oxide layers, which reduce electrical conductivity and compromise system efficiency. Additionally, they require high hydrophilicity to improve gas-liquid contact and mass transfer. To address these challenges, these components are often coated with thick layers (~200nm) of precious metals such as platinum or gold, increasing costs significantly [2].

In this work, titanium nitride (TiN) coatings are investigated as a cost-effective alternative to conventional Pt or Au coatings on PTLs, aiming to provide high corrosion resistance, conductivity, and hydrophilicity [3,4]. Three gas-phase coating techniques to make TiN are explored in this work: atomic layer deposition (ALD), reactive sputtering (physical vapor deposition), and direct plasma nitridation. ALD offers excellent coating conformality and high penetration depth but involves a more complex and time-intensive process. In contrast, reactive sputtering is a simpler and more cost-effective method, though it can compromise coating conformality. The conformality achievable with direct plasma nitridation remains uncertain and requires further evaluation.

Initial studies involved TiN film deposition on silicon wafers to evaluate coating quality, followed by application on 3D PTL structures. Electrochemical testing was first conducted in a three-electrode setup, after which the coated PTLs were evaluated under PEM water electrolysis conditions. The results of our work demonstrate the potential of titanium nitride coatings as a scalable protective layer for PEM water electrolysis components, offering a pathway toward cost-effective and efficient green hydrogen production.

References

[1]U. Babic et al., J. Electrochem. Soc., 164(4), F387, 2017.

[2]T. Srour et al., Int. J. Hydrog. Energy, 58, 351-361, 2024.

[3]G. Liu et al., Int. J. Hydrog. Energy, 48(50), 18996-19007, 2023.

[4]N. Rojas et al., Int. J. Hydrog. Energy, 46(51), 25929-25943, 2021.

This project receives a Dutch National Growth Fund contribution from the NXTGEN programme HIGH-TECH.

The modern trend of semiconductor device design approaching increasingly smaller scales, alongside the desire for devices to be integrated into complex three-dimensional architectures, has caused an industry-wide need for precise control over film quality and interface properties. The interface between bottom electrode materials and dielectric layers is of particular interest as the thickness of a modern dielectric decreases to the single nanometer range. Ru is a well-studied bottom electrode material for dynamic random-access memory applications, in part due to its low bulk resistivity (7.1 µΩ cm) and high work function (4.7eV). Unfortunately, during oxidation cycles of dielectric ALD the industry standard O₃ exposure often causes the formation of volatile RuO₄. The result of this oxidation effect being lower quality Ru-based interfaces with etched RuO₂. In previous semiconductor generations this surface roughness for a bottom electrode interface would be a minor concern, but as modern semiconductor designs demand thinner films, the need for a higher quality and uniform interfaces has become pertinent.

Here we showcase evidence of higher quality uniform RuO₂ thin film formation via BRUTE Peroxide (high concentration H₂O₂)exposure, mitigating the formation of RuO₄. We compare these films to comparable O₃ exposed Ru/RuO₂ films and as-deposited Ru films. Resulting structures are characterized through scanning electron microscopy surface imaging, x-ray reflectivity and x-ray photoelectron spectroscopy analysis, among other techniques.

Continued scaling of semiconductor interconnects has led to increased RC delay, reduced Cu volume, size-effect-induced resistivity increase, and degraded electromigration reliability. Conventional Cu interconnects rely on complex TaN/Ta diffusion barrier and liner stacks. However, this multilayer scheme faces severe scaling limitations, thereby motivating the search for alternative diffusion barrier and liner materials. Transition-metal nitrides (TMNs) especially niobium nitride (NbN) offer high melting point (≈2400 °C), strong chemical stability, and metallic conductivity (58–78 μΩ·cm), making them suitable diffusion barrier candidates for advanced interconnect integration [1] [2]. As interconnect dimensions continue to shrink, atomic layer deposition (ALD) becomes essential due to its self-limiting surface reactions, excellent conformality, and precise thickness control in high-aspect-ratio device structures. In this study, we investigate the ALD feasibility of NbNₓ thin films using a novel liquid Nb precursor, which offers higher volatility and stable vapor delivery compared with conventional solid precursors such as NbCl₅ or NbF₅. Multiple reactants including NH₃ molecule, NH₃ plasma, N₂ plasma, and N₂:H₂ mixture plasma were examined to identify effective nitridation pathways. Among them, NH₃ plasma was the only reactant capable of forming crystalline NbNₓ and further experiments were done mainly using NH₃ plasma. The ALD-NbN_x process was conducted in a showerhead-type PEALD reactor (IOV dX1 PEALD, ISAC RESEARCH, Korea). Self-limiting growth behavior was confirmed through both precursor and reactant pulsing time, with a saturated growth rate of approximately 0.18 Å/cycle. A stable ALD temperature window was identified between 250–350 °C, with the best film quality achieved at 300 °C. The properties of ALD-grown NbNₓ films were characterized using XRD, XRR, SEM, XPS and TEM. Finally, the ALD-grown NbNₓ films were evaluated as diffusion barrier for Cu and Ru interconnects, demonstrating their potential for advanced interconnect applications. Detailed barrier performance results will be presented at the conference.

References

[1] Pierson, H. O., Handbook of Refractory Carbides and Nitrides, Noyes Publications.

[2]Klug et al., J. Phys. Chem. C, 2011, 115, 25063–25071.

Acknowledgements

This work was supported by the Korea Institute for Advancement of Technology (KIAT) grant funded by the Korean Government (MOTIE) (P0028867, HRD Program for Industrial Innovation). This work was also supported by the Industrial Strategic Technology Development Program (RS-2024-00509266, Development of next-generation dielectric, electrode process equipment, and core materials for logic 1 nm or less and memory × nm level), funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea).The precursor used in this study was provided by SK trichem Co., Ltd., Korea.

Top-gated MoS₂ FETs require conformal, ultrathin high-k dielectrics with low interface trap density [1]. However, the surface-limited reactions in atomic layer deposition (ALD) can also perturb MoS₂ channel chemistry, degrading electrostatic control and limiting reproducibility [2]. It is thus critical to establish a process-channel framework that decouples nucleation-driven interface formation from channel-damaging reactions. In this work, we examine how MoS₂ film quality governs top-gate insulator integration and defines the boundary between chemistry-enabled interface improvement and defect-activated channel damage.

We first established a single-crystal benchmark using mechanically exfoliated few-layer MoS₂. Comparative oxidant studies show that H₂O₂-based ALD of HfO₂ yields improved gate controllability relative to conventional oxidants (H₂O, O₃), consistent with a chemically stabilized interface associated with S-O bond formation. These results indicate that oxidant engineering can overcome the conventional nucleation-interface-quality tradeoff without relying on seed or interfacial-layer strategies, providing a practical route for scaled top-gated 2D devices.

We then extend the same gate-stack process to wafer-scale MoS₂ films from multiple sources (e.g., chemical vapor deposition (CVD)- and chemical vapor transfer (CVT)-grown). In contrast to exfoliated single-crystal flakes, large-area MoS₂ exhibits overall degradation after high-k deposition, indicating that film non-idealities and spatial variability dominate the integration outcome. We attribute this divergence to defect-mediated interfacial chemistry, where abundant reactive sites in wafer-scale MoS₂ promote localized oxidation and non-ideal bonding even under H₂O₂-enabled deposition, thereby degrading transport and gate controllability. This trend further suggests that defective MoS₂ films require milder ALD windows (e.g., lower temperature and reduced oxidant reactivity) to suppress defect-activated parasitic reactions while preserving nucleation.

Overall, this study establishes process-structure-property relationships linking MoS2 quality to top-gate dielectric integration and provides actionable design rules for reliable 2D FET gate stacks toward future 3D-integrated electronics.

This work was supported by Samsung Electronics through GRO program (IO250621-13116-01) and the KEIT grant funded by MOTIE (RS-2023-00235484, No, 1415187770). The ozone generator was provided by TMEIC, and the BRUTE® Peroxide was provided by RASIRC Inc.

[1] S. Das et al. Nat. Electron. 4, 786–799 (2021).

[2] J.-S. Ko et al. Nano Lett. 25, 2587–2593 (2025).

Cerium oxide (CeO₂) is a rare-earth oxide with a high dielectric constant, moderate bandgap, excellent chemical stability, and multiple valence states (Ce³⁺/Ce⁴⁺). Owing to these properties, CeO₂ has been widely investigated for applications such as CMOS gate dielectrics, SOFCs, gas sensors, and resistive switching memories. The formation of CeO₂ requires complete oxidation of Ce³⁺ to Ce⁴⁺, which demands a relatively high oxidation potential. However, under low-temperature ALD conditions,the limited oxidation capability of conventional O₂- and H₂O-based oxidants often results in degraded film quality due to incomplete oxidation and residual organic species.To overcome these limitations, O₃ was selected as the oxidant in this study. Ozone (O₃) generates highly reactive oxygen species upon decomposition, providing strong oxidation capability and enabling effective low-temperature oxidation without plasma assistance. In this work, CeO₂ films were deposited by ALD (IOV dX1 PEALD reactor, ISAC Research, Korea) using aheterolepticcyclopentadienyl-amidinate Ce precursor and O₃ as the reactant. As shown in Figure 1, CeO₂ films deposited using O₃ exhibit stronger diffraction peaks than those grown with conventional oxidants (H₂O, O₂, and O₂ plasma), indicating improved crystallinity. The deposition temperature was conducted at temperatures ranging from 150 to 350 °C, with 200 °C determined as the optimal growth temperature. The self-limiting growth behavior was shown with both precursor pulsing and reactant pulsing and the saturated growth-per-cycle (GPC) was approximately 1.15 Å/cycle. Film properties varied with deposition conditions and were characterized by SEM (thickness), TEM (step coverage, thickness), XRR (density and thickness), XRD (crystallinity), XPS (composition) and RBS (impurity). Electrical properties were evaluated via Metal–Oxide–Semiconductor capacitors, focusing on dielectric constant and leakage current. The detailed results will be presented at the conference.

Acknowledgements

This work was supported by Korea Institute for Advancement of Technology (KIAT) grant funded by the Korea Government (Ministry of Education) (P0028867). This work was also supported by the Industrial Strategic Technology Development Program (RS-2024-00509266, Development of next-generation dielectric, electrode process equipment, and core materials for logic 1 nm or less and memory x nm level), funded by the Ministry of Trade, Industry & Energy (MOTIE, Korea). The precursor used in this study was provided by UP Chemical Co. Ltd, Korea.

Nanometer-thick TiO₂-channel thin-film transistors (TFTs) are promising not only as high surface-sensitive sensors but also as active-matrix switching devices. InGaZnO (IGZO) has been used as a high-mobility TFT channels, offering around 10 cm²/Vs. However, IGZO includes rare metals such as indium and gallium, leading to issues related to high cost geopolitical risks. On the other hand, TiO₂ is abundant on earth, non-toxic, although the field effect mobility of TiO₂-TFT was reported to be low due to defects in the film. In this study, the drain current enhanced TiO₂ TFTs were developed using atomic layer deposition.

We fabricated TiO₂-TFTs with a channel thickness of 16 nm as shown in Fig. 1, in which the channel surface was covered with an aluminum-silicate and SiO₂ periodical stacks. The stack layer serves as both the alkali metal absorber in the chloride solution and the meal diffusion source. The TiO₂ channel was deposited by atomic-layer deposition, followed by being annealed in dry air to induce crystallization. TFT samples were immersed in the alkali metal chloride solution, and it was assumed that the adsorbed metals were automatically diffused to the channel layer, which might contribute to deactivating the defects in the channel layer.

We confirmed the enhanced drain currents with CsCl and NaCl solutions as shown in Fig. 2. This suggests their potential as a high-mobility TFT. The effective mobility was calculated to be 83 and 46 cm²/Vs for Cs and Na, respectively. XPS measurements suggested a reduction of TiO₂, which might contribute to the deactivation of the Oxygen-deficiency-related defects in the TiO₂ channel layer. In the conference, we shall discuss the current enhancement mechanism and applicability as an active-matrix switching devices.

Dynamic random-access memory (DRAM) has been continuously scaled down to reduce production costs and increase integration density, thereby reducing the area occupied by cell capacitors and decreasing cell capacitance. This decrease in cell capacitance reduces sensing margin in read operations. Therefore, a material with a higher dielectric constant (k) is required as an insulator in DRAM capacitors to recover cell capacitance. TiO₂ in the rutile phase is an attractive candidate due to its high k value (>100) and compatibility with atomic layer deposition. However, it has leakage current issues due to its small bandgap (~3 eV). Therefore, suppressing leakage current via conduction band offset control between TiO₂ and the electrode film, such as Al doping, was effective. However, Al doping significantly decreases the capacitance density of TiO₂.

In this work, we evaluated the effectiveness of Mg, Sc, Gd, and In as alternative dopants for replacing Al. Crystallinity of each doped TiO₂, as a function of dopant and concentration, was analyzed by grazing-incidence X-ray diffraction, and the trend was consistent with dopant formation energy results obtained from density functional theory (DFT)-based simulations. Additionally, we evaluated the electrical properties of each doped TiO₂ and elucidated the dopant-dependent mechanism of electrical properties changes using X-ray photoelectron spectroscopy analysis and DFT simulations. Consequently, the Sc dopant did not significantly degrade the dielectric constant of TiO₂ among dopant candidates, thereby further improving the electrical properties by controlling the Sc doping concentration gradient.

References [1] W. Jeon, J. Mater. Res. 35, 7 (2020).

Three-dimensional NAND (3D NAND) memories demand charge-trap stacks that provide wide memory windows at low programming voltages for reliable multi-level cell operation and reduced cell-to-cell interference. Hafnium oxide (HfO₂) has emerged as a promising charge-trap layer material because of its high dielectric constant and strong trapping capability.[1]However, uncontrolled intrinsic defects and non-uniform trap distributions in pristine HfO₂ often lead to leakage current and unstable charge storage.

To address these issues, previous studies have reported that Gd doping was employed to engineer the trap characteristics of HfO₂.[2]The substitution of Hf⁴⁺ by Gd³⁺ induces local lattice distortion and defect complexes, which suppress shallow oxygen-vacancy-related traps and generate energetically deeper trap states. These deep traps enhance charge confinement and suppress leakage pathways, resulting in an enlarged memory window and improved retention characteristics.

In this work, Al₂O₃/HfO₂/Al₂O₃ capacitors with Gd-doped HfO₂ layers (1–10%) were fabricated and evaluated using incremental step pulse programming. The 5% Gd-doped HfO₂ stack exhibited the widest memory window and the most efficient programming behavior, indicating an optimal deep trap density for charge storage. Electrical measurements further revealed that Gd doping improves the blocking characteristics by reducing leakage current, thereby enhancing charge retention performance.

Post-metallization annealing at 400 °C significantly modified the trap distribution, promoting the formation of deeper trap states and improving programming efficiency. In contrast, excessive Gd doping (≥10%) led to degraded hysteresis behavior, suggesting leakage-dominated transport due to excessive defect generation.

These results demonstrate that Gd-induced deep trap engineering, combined with thermal processing, provides an effective strategy for optimizing HfO₂-based charge-trap stacks, enabling low-voltage, wide-window, and high-reliability operation for future 3D NAND flash memory applications.

References

[1] You & Cho et al., Appl. Phys. Lett. 96 093506 (2010)

[2] Y. Shen et al., RSC Adv. 10, 7812–7816 (2020)

As dynamic random-access memory (DRAM) devices continue to scale down, the reduction of equivalent oxide thickness in cell capacitors has become increasingly critical, necessitating the use of high-k dielectric materials. Rutile-phase TiO₂ is a representative high-k material with dielectric constant of approximately 100 or higher; however, its relatively narrow bandgap and donor levels associated with oxygen vacancies lead to high leakage current. Therefore, acceptor doping using trivalent cations, particularly Al, has been investigated as an approach to reducing leakage current.

In this study, we propose a new approach to effectively suppress leakage current through grain boundary in TiO₂. Grain boundary is defect-rich regions where electron accumulation can readily occur, thereby acting as leakage current conduction paths. To suppress leakage current through grain boundary, La was doped to induce segregation toward grain boundary. Because La³⁺ has a larger ionic radius than Ti⁴⁺, its substitution into the TiO₂ lattice is limited, and this significant ionic radius mismatch can promote preferential segregation of La at grain boundary. After La doping, post-deposition annealing (PDA) was performed to induce La segregation. Grazing-incidence X-ray diffraction analysis revealed that the rutile TiO₂ peak shifted toward higher angles after PDA at 600 °C compared to the as-deposited state. This shift indicates a reduction in the d-spacing of TiO₂ as La initially present within the lattice migrated to grain boundaries during annealing, supporting the occurrence of La grain boundary segregation. Furthermore, electrical characterization showed a significant reduction in leakage current in La-doped TiO₂ dielectrics, which is attributed to the effective suppression of grain-boundary-related conduction paths. These results suggest a novel mechanism for reducing leakage current in rutile TiO₂-based high-k dielectrics and provide a promising approach for next-generation DRAM capacitor applications.

References

[1] W. Jeon et al., ACS Appl. Mater. Interfaces. 6, 10,7910–7917 (2014)

[2] Q. Wang et al., Acta Mater. 52, 4, 809 (2004)

This study reports on the development of novel organosilicon precursors specifically tailored for the atomic layer deposition (ALD) process of silicon oxicarbide (SiOC) thin films. First, to design precursor structures effective for ALD, we established a computational framework for systematically evaluating the adsorption energy, activation energy, and reaction energy of precursors. This enabled the selection of an optimal precursor structure with a stable Si-C-Si backbone. Subsequently, we successfully synthesized the precursor based on a unique chemical path. The resulting ALD of the precursor demonstrated obviously higher growth per cycle (GPC) compared to conventional precursors, and the ALD film included Si-C-Si bonds well. Furthermore, by analyzing dependency of process temperature, precursor dose time, and ozone dose time, ALD based film growth mechanism was clarified. A notable challenge in high–temperature ALD processes is that the carbon concentration in the film generally decreases as process temperature increases. Moreover, process modifications aimed at increasing the carbon ratio typically led to a deterioration in both GPC and in–plane uniformity. In this work, however, by carefully optimizing the process conditions, we successfully achieved high carbon concentration, high GPC, and good in–plane uniformity simultaneously, even under high–temperature deposition conditions.

Since the discovery of negative capacitance (NC) in ferroelectrics, extensive research has been conducted in the field, with the Negative Capacitance Field-Effect Transistor (NC-FET) emerging as a breakthrough technology. NC-FETs have attracted significant attention for their ability to lower the subthreshold swing (SS) below the fundamental limit of 60 mV/dec at room temperature, making them highly advantageous for suppressing leakage current and realizing ultra-low-power devices.

In our previous study [1], we successfully deposited (HZO) ferroelectric thin films with relatively good polarization and reliability characteristics using a Co-Plasma ALD (CP-ALD) process, which simultaneously utilizes both direct and remote plasmas, as shown in Fig. 1. However, the inherent polarization hysteresis of ferroelectrics remains a significant challenge for switching device applications. To precisely control the NC characteristics, optimized capacitance matching through a ferroelectric-dielectric (FE/DE) stacked structure is essential [2].

Based on the characteristics of the HZO thin films deposited via our group’s CP-ALD process, we modeled the electrical performance of MFIS-structured NC-FETs by stacking ferroelectric and dielectric layers, as illustrated in Fig. 2(a). For a 15-nm-thick ferroelectric HZO layer, the subthreshold swing (SS) was modeled as a function of the dielectric layer thickness, using Al₂O₃(k9) and HfO₂(k25) as the dielectric materials.

The results indicate that sub-60 mV/dec SS values are achieved when the dielectric thickness is below 1.4 nm for Al₂O₃ and 5.4 nm HfO₂. In particular, the most stable and lowest SS values were observed at thicknesses of 1.4 nm for Al₂O₃ and 3.8 nm for HfO₂. Especially, HfO₂ exhibited a much broader thickness window for maintaining an SS below 60 mV/dec compared to Al₂O₃. The optimized SS of the NC-FET improved by up to 12 mV/dec compared to that of a conventional MOSFET without a ferroelectric layer.

Additionally, to analyze the NC phenomenon in a practical polarization-switching environment, we will present modeling results based on the Nucleation-Limited Switching (NLS) theory, which accounts for the time-dependent transient polarization characteristics of ferroelectrics.

Acknowledgments: This work was supported by Next-generation Intelligence Semiconductor Foundation grant funded by the Korea government (the Ministry of Science and ICT, the Ministry of Trade, Industry and Energy) (Grant No. 2410011349, RS-2024-00407627) and by the K-CHIPS(Korea Collaborative & High-tech Initiative for Prospective Semiconductor Research) (2410011219, RS-2023-00237030, 23027-15FC) funded by the Ministry of Trade, Industry & Energy(MOTIE, Korea).

References

[1] W.J. Park, H.J. Kim, J.H. Lee, J.H. Kim, S.H. Uhm, S.W. Kim, H.C. Lee, Nanomaterials 14(22) (2024) 1801.

[2] M. Si, C.J. Su, C. Jiang, N.J. Conrad, H. Zhou, K.D. Maize, G. Qiu, C.T. Wu, A. Shakouri, M.A. Alam, P.D. Ye, Nature Nanotechnology 13 (2018) 24–28.

As Dynamic random-access memory (DRAM) capacitors continue to scale down, capacitance loss and increased leakage current become critical challenges, necessitating high-k dielectrics with improved phase stability. HfO₂ is widely used due to its high dielectric constant and adequate bandgap;[1] however, its stable monoclinic phase limits further equivalent oxide thickness (EOT) scaling, and stabilization of the tetragonal HfO₂ phase is therefore required.[2]

In this work, vanadium oxide (VO_x) was employed as an interfacial layer to modulate the interfacial oxygen environment and promote tetragonal HfO₂ formation. VO_x films were deposited by atomic layer deposition, and their oxidation states were analyzed by X-ray photoelectron spectroscopy as a function of process temperature. At 150 °C, the VO_x film exhibited a V⁵⁺-dominant composition (84.22%, O:V = 2.88), whereas increasing the temperature to 300 °C increased the V⁴⁺ fraction to 58.07% (O:V = 2.16), indicating controllable oxidation-state tuning from V₂O₅-like to VO₂-like.

When an ultrathin VO_x interlayer (1–2 nm) was inserted between TiN and HfO₂, the tetragonal HfO₂ phase emerged after annealing, while no tetragonal phase was observed without VO_x. Post-annealing of VO_x at 500 °C revealed that VO₂(M) crystallization occurred only under an oxygen partial pressure of 25 mTorr, whereas higher oxygen partial pressures led to excessive oxidation and V₂O₅ formation.

In TiN/HfO₂/VO_x/TiN structures, the tetragonal HfO₂ fraction exhibited a dome-shaped dependence on oxygen partial pressure, reaching a maximum when the VO_x interlayer was VO₂-like (V⁴⁺-dominant). These results demonstrate that oxidation-state-engineered VO_x effectively regulates interfacial oxygen vacancy conditions, enabling stable tetragonal HfO₂ formation and providing a viable pathway for advanced DRAM capacitor scaling. Such stabilization of the tetragonal HfO₂ phase is expected to enhance the effective dielectric constant, enable further EOT scaling, and improve leakage current characteristics through optimized oxygen vacancy control.

References

[1] W. Jeon, J. Mater. Res. 35, 7 (2020).

[2] Y. U. Ryu et al., Ceram. Int. 50, 21, 41483 (2024).

Proton exchange membrane water electrolysis (PEMWE) is considered a highly promising technology for converting intermittent renewable electricity into green hydrogen, yet it relies on scarce platinum-group metal for their catalytic activity and chemical stability, which could significantly limit scalability. The porous transport layer (PTL) is a critical component, typically made of titanium, on the anode of PEM electrolysers, since it facilitates the electron and mass transfer between the catalyst sites and the bipolar plates. A major challenge stems from the oxidation of the PTL in the highly oxidative anodic environment, which significantly reduces electrical conductivity and limits catalyst utilization. To protect the contact points between the anodic layers, the commercial solution involves the platinization of the PTL. However, this approach not only increases further the manufacturing costs, but also results in poor coating conformity thus risking its long-term durability.

This study investigates the use of ALD to achieve a conformal and uniform Pt coating on the PTL surface, in combination with evaporation to increase the coating thickness. We examine how the Pt loading, morphology, and thickness affect the performance and durability of the layer in a 4 cm² single PEM cell, identifying which coating configuration provides optimal protection for the PTL. Finally, we evaluate the deposition of iridium oxide to transform the PTL into a porous transport electrode and assess its electrochemical performance.

This project receives a Dutch National Growth Fund contribution from the programme NXTGEN HIGHTECH.

Atomic Layer Deposition (ALD) enables precise control of layer thickness at the atomic level, making it more suitable than Chemical Vapor Deposition (CVD) for etch stop layers (ESLs) in advanced transistor manufacturing. ESLs are crucial for precise pattern transfer and underlying structures protection during etching. As device dimensions continue to scale, there is an increasing demand for ultrathin and uniform ESLs with well-controlled thickness and etch selectivity.

In this work, we investigate the use of SiCO layers deposited by Single Precursor Activated Radicals Chemistry ^[1] (SPARC) process (a new technique in-between CVD and ALD), as SiN dry etch stop layer for MOL (middle of line) and BEOL (back-end of line) applications. We focus on the impact of the carbon elemental composition on the SiCO layer’s resistance to standard wet clean chemistries and its ability to maintain ESL properties under etching plasma exposure.

We use 30nm thick SiCO layers, deposited at 400°C, with carbon content varying from 3% to 13%. We characterize the material resistance to standard wet clean chemistries and to two plasma etching chemistries (CH3F/O2/Ar and CH3F/H2), by monitoring the layer thickness before and after the process steps using a spectrometric ellipsometer. We assess the impact of the etching plasma on the remaining SiCO material through Secondary Ion Mass Spectrometry (SIMS) elemental depth profiles.

Results show that SiCO layers exhibit high resistance to wet clean chemistries, with minimal thickness loss observed only in low carbon content films exposed to diluted HF, and its resistance increases as the carbon composition increases. After exposure to the plasma chemistries used for SiN dry etch, all SiCO layers show thickness reduction, with oxygen-based plasma causing greater removal than hydrogen-based plasma. Plasma etching modifies a few nanometers of the remaining SiCO film, which becomes an O-rich layer that can be removed with a dHF dip. The altered layer thickness is more substantial with hydrogen-based plasma, and higher carbon content results in shallower modifications.

These findings show that this SiCO layer deposited by SPARC is a promising material for MOL and BEOL ESL applications as it has a high resistance to both dry and wet etching processes while being easily removable after undergoing a plasma etch.

The authors would like to thank Lam Research for their contribution to this work. This work was carried out within the Fames Pilot Line of the Chips JU, funded by Horizon Europe grant 101182279 and the ANR NextGen project ANR-22-NEXTG-001 of the France 2030 initiative.

^[1] Patent WO 2018/111627 Al

Atomic layer etching (ALE) offers sub-nm level control over film removal and presents promising solutions to address patterning challenges in device manufacturing. These mechanisms become particularly important when the extended atomic structure of films such as crystal facets, grain boundaries, and dopants are taken into consideration.

In this work, we investigate the thermal ALE of aluminum doped zinc oxide (Al:ZnO) using β-diketonate-etchants such as, acetylacetonate (Hacac) and hexafluoro acetylacetonate (HFacac), by depositing monolayers of Aluminum into Zinc oxide. We utilize in situ spectroscopic ellipsometry (SE) and quadrupole mass spectrometry (QMS), enabling real time correlation between thickness evolution and reaction by-products. By coupling these techniques, this work provides insight into kinetics, reaction pathways, and the role of dopants.

Research on low-κ dielectric materials is becoming critically important to deal with capacitance delays of due to decreasing dimensions of integrated circuits. Herein, we will report the structural and dielectric properties of terpineol-doped Al₂O₃ films where terpineol acts as a sacrificial agent or porogen, leaving porosity in the films after post-deposition annealing treatment. Terpineol-doped films were deposited by atomic layer deposition (ALD) and the modification of the porosity by changing the ratio of terpineol pulse in between the metal precursor and H₂O co-reactant was explored. The choice of metal precursor also influences the porosity generation in the film because of the steric hindrance and reactivity of the precursor. Three metal precursors, trimethylaluminum (TMA), aluminum tri-sec-butoxide, and tri-i-butylaluminum will be used to study the density, dielectric constant of the films. X-ray reflectivity will be used to measure the density of the films. For TMA to terpineol ratio 1:1, initial result showed 17% decrease of density for as deposited terpineol doped films than ALD Al₂O₃ at 120°C. Dielectric constant of the films will be measured using capacitance-voltage measurement. For as-grown terpineol-doped films the initial measurement also showed dielectric constants as low as 4 compared to a value of ~7 for ALD grown Al₂O₃. Our work shows that small molecule inclusions in ALD is a useful strategy for the growth of porous and low-κ thin films, while still retaining the benefits of precise thickness control and conformality afforded by ALD.

Gallium Nitride (GaN) has recently expanded into power electronics, RF,microLEDs and VCSELsmarkets.The adoption of GaN transistors in high volume consumer-based power electronicsis driven by the need for smaller, faster, efficient mobile device chargers.It has been predicted the GaN power device market will reach $3B by 2030¹supported by a broader range of applications including renewable energy, data centres, electric vehicles, and infrastructure for 5G and 6G networks.

These emerging GaNmarkets require uniform,conformal,low damage plasma processing solutions optimised for 200 mm wafers to improve device performance,throughput, andyieldat reduced cost.Plasma enhanced atomic layer deposition (PEALD) has been used in GaN transistors for low damage,²uniform passivation layers (Al₂O₃,³ SiN), as a method of optimizing the interface using native oxide removal nitridation^4,5followed by deposition of high-quality nitrides like AlN.

High throughput plasma ALD of SiN is beneficial for GaN device processing at low temperature (≤500 °C) compared to LPCVD (≥700 °C)and thermal ALD (>450 °C) without compromising on conformality (compared to PECVD)¹⁰or uniformity up to 200 mm wafer size. PEALD SiN has also been shown to reduce trap defect density in GaN transistors compared to other deposition techniques and materials.¹¹Optimisation of the plasma processing parameter scan achieve SiN films with tuneable growth rate,composition,and refractive index.^{12, 13}.

PEALD processes forAlN and SiN have been developed achieving excellent thickness and refractive index uniformity across 200 mmSi wafers using Oxford Instruments Atomfab ALD system which uses apatented capacitively coupled (CCP)³ remote plasma source. Using Oxford Instruments’ novel CCP remote plasma source, and a low chamber volume, increase in deposition rate has been achieved when comparing to an inductively coupled plasma source (ICP) process. For example, we have been able to achieve 8 times faster deposition rate for AlN films using our CCP remote plasma source compared to ICP plasma.The composition of the AlN and SiN films were measured by XPS resulting in low C% and O% content. The ToF-ERDA showed low H% content in SiNx films while the wet-etch rate was better for the films produced using the CCP plasma source compared to the films produced by ICP plasma source. The breakdown voltage and the dielectric constant for the as deposited SiNx film obtained was >10.5 MV/cm and >6 for 30 nm film respectively.

To support the production ramp of the GaN transistors, high throughput tuneable AlN and SiN processes using plasma ALD along with optimized surface pre-treatment has been developed by Oxford Instruments negating the need for extended plasma exposure,high temperature depositionor temperature ramping within the process.The estimative wafers produced per hour for AlN (3 nm films) is 11 WPH and for SiNx (5 nm films) is 10 WPH.

Charge trap memory devices employing a sputtered CAAC IGZO channel were fabricated using an Al₂O₃/HfO₂/Al₂O₃ dielectric stack as the blocking, charge trapping, and tunneling layers. All dielectric layers were deposited by remote plasma atomic layer deposition, while the CAAC IGZO channel was formed by sputtering to preserve its crystalline–amorphous composite structure. The electrical characteristics of the devices were systematically compared with those incorporating dielectric layers deposited by direct plasma ALD. Devices with remote plasma–processed dielectrics exhibited an enlarged memory window and reduced leakage current. Material analysis revealed a decreased concentration of oxygen vacancies in the HfO₂ charge trap layer for the remote plasma ALD process compared to direct plasma ALD. In addition, remote hydrogen plasma treatment was employed at the channel–tunneling layer interface, effectively passivating interfacial defects between the CAAC IGZO channel and the Al₂O₃ tunneling layer. This interfacial defect reduction enhanced charge injection and trapping efficiency. The combined effects of reduced bulk defects in HfO₂ and improved interfacial quality in the dielectric stack contribute to enhanced charge storage characteristics in CAAC IGZO–based memory devices.

This work was supported by K-CHIPS(Korea Collaborative & High-tech Initiative for Prospective Semiconductor Research) (2410011219, RS-2023-00237030, 23027-15FC) and by the Technology Innovation Program (Materials & Components Technology Development (R&D)– Package-type) (RS-2025-02220734, Development of Manufacturing Technology for High-Purity iron chloride (>99.5%) and Sodium Silicate (>97.0%) via Utilization of Bayer Process Byproducts) funded By the Ministry of Trade Industry & Energy(MOTIE, Korea).

The scaling of advanced DRAM technologies requires complex structures with high aspect ratio (HAR) trenches and cavities and is currently transitioning to 3D integration to sustain performance improvements.^[1] Hafnium based oxides are key materials for the cell capacitor in DRAM cells due to their high dielectric constant and wide bandgap. To achieve conformal growth in HAR structures, ALD processes often use large precursor and oxidant doses to ensure reactant transport into deep features ^[2]. However, excessive oxidant dosing can promote undesirable interfacial oxidation, particularly on metal electrodes. To address this, we identify differences in oxidant efficiency during HAR filling and evaluate the role of various counter-reactants on conformal growth.

To understand the effect of counter reactant choice, we first investigated growth characteristics on planar substrates. We found that the oxidant dose required to reach saturation was different for each oxidant. Namely, we found that H₂O₂ required a smaller dose than O₃ to saturate each ALD cycle. Saturation at a reduced oxidant dose implies a potential for improved filling in HAR structures at lower doses while mitigating excessive interfacial oxidation due to high dosing.

Based on the observations for planar substrates, vertical HAR substrates with AR ranging from ~20:1 up to ~60:1 were used to evaluate the conformality of each process. Furthermore, to enable quantification of penetration depth, specially designed horizontal Ultra-HAR structures with AR up to 10,000:1 were used, and analysis of growth areas were performed using SEM and EDX (Fig. 1). The extent of growth into the cavity was used to assess the deepest achievable filling as a function of both oxidant and precursor dosing. Alongside the horizontal structures, conformality was also evaluated in vertical trenches with smaller critical dimensions, providing access to more extreme confinement where precursor transport is further limited (Fig. 2). We found that increasing precursor dose improves transport into confined geometries, with signatures of oxidant-dependent effects on HAR filling. Overall, these results show that oxidant choice plays an important role in ALD growth in HAR structures for the stringent demands of next-gen semiconductor devices.

We acknowledge RASIRC for providing BRUTE^® Peroxide and TMEIC for providing the ozone generator (OP-250H). This work was supported by Samsung Electronics Co., Ltd. (No. IO221018-03002-01). We would also express our gratitude to Chipmetrics for providing the UHAR substrates.

1. Yoon, C et al., Nanomat. 2025, 15, 783
2. Gordon R. et al., Chem Vap Deposition 2003, 9, 73-78

As dynamic random-access memory (DRAM) scales down to achieve higher integration, electrode engineering to mitigate insufficient capacitance and excessive leakage current remains a critical challenge. TiN electrodes and ZrO₂ dielectrics are widely used in metal-insulator-metal (MIM) capacitors because of their excellent process compatibility. However, TiN electrodes deplete oxygen from ZrO₂ at the ZrO₂/TiN interface via an oxygen-scavenging effect, forming undesirable TiO_xN_y. This accelerates leakage and degrades performance.[1] The formation of these oxygen defects degrades not only the electrical characteristics but also the overall performance of the MIM capacitor. The initial spacing is not correctly formatted. Furthermore, nitrogen diffusion into ZrO₂ reduces the bandgap, resulting in degradation of leakage current characteristics.[2] Therefore, oxide-based electrodes are more suitable for use with ZrO₂ than nitrogen-based electrodes. To overcome these limitations, we propose an approach that uses Mo-doped In₂O₃ bottom electrode grown by atomic layer deposition (ALD). During thermal treatment, Mo-doped In₂O₃ exhibits a change in oxidation state to Mo⁴⁺, which substitutes for In³⁺, resulting in high electrical conductivity due to increased free electrons and low resistivity. [3] Furthermore, its low roughness provides excellent electrode characteristics for MIM capacitors. [4] In terms of crystallinity, here to, the initial spacing is incorrect. The cubic phase In₂O₃ (400), formed by Mo doping in In₂O₃, exhibits good crystallographic compatibility with the tetragonal phase ZrO₂ (002). The formation of t-ZrO₂ (002) enables higher capacitance in ZrO₂-based MIM capacitors fabricated on Mo-doped In₂O₃. The high work function (~5 eV[5]) of Mo-doped In₂O₃ provides a distinct advantage over TiN (~4.2 eV[6]). This high work function contributes to leakage suppression, thereby enhancing the device's overall performance. Additionally, In₂O₃ has a significantly lower oxygen vacancy formation energy (~2.4 eV) than ZrO₂(~6.2 eV), enabling oxygen transfer to ZrO₂.[5] This mechanism not only suppresses the formation of sub-interface oxides, unlike TiN electrodes, but also reduces defect density within the ZrO₂ layer, minimizing unwanted conduction and improving interface stability. Consequently, replacing TiN with the ALD-grown Mo-doped In₂O₃ bottom electrode offers a practical, scalable solution. Mo-doped In₂O₃ provides sufficient capacitance while suppressing leakage current and enhancing stability, thereby strengthening the integrity of the MIM capacitor structure. This paves the way for continued dielectric scaling and improved reliability in advanced DRAM technology.

References [1] W. Jeon, J. Mater. Res. 35, 7 (2020). [2] Matei, et al., Front. Chem. 11 (2023): 1239964. [3]Catalán et al., Appl. Surf. Sci. 386 (2016): 427-433. [4] Chung, et al., Appl. Surf. Sci. 610 (2023): 155526. [5] Y. choi et al., Appl. Surf. Sci., (2025) 164149. [6] Kim et al, Electron. Mater. Lett, (2025) 1-9.

Like 3D NAND scaling progresses, the integration of 3D DRAM and advanced logic architectures requires highly conformal dielectric gap–fill capability within increasingly complex high–aspect–ratio structures. Conventional deposition schemes optimized for vertical profiles exhibit insufficient step coverage in lateral cavities, resulting in seam and void formation due to precursor transport limitations and restricted surface reaction accessibility. Moreover, the enlarged effective surface area significantly reduces throughput, forcing reliance on iterative deposition–etchback cycles that remain inefficient and inherently unsuitable for uniform lateral gap–fill.

To overcome these limitations, a novel ALD based gapfill strategy has been developed, enabling fully seamless void free filling across both vertical and lateral geometries. TEM analysis confirms that while conventional processes show pronounced internal seams shown in Fig. 1 (a), the newly engineered process demonstrates complete elimination of interfacial defects, ensuring structurally dense and continuous films throughout the entire 3D topology in Fig. 1 (b). This approach delivers improved structural robustness, enhanced conformality, and high productivity, positioning it as a key enabling technology for next generation high density 3D device fabrication.

As AI technology advances and the need for high-performance memory semiconductors increases, 3D DRAM manufacturing technology is one of the promising technology to increase memory capacity. To reduce high experimental costs and increase process development speed, it is important to estimate processing time in the atomic layer deposition process. As the number of lateral trenches increases, the adsorption area increases compared to when there are only vertical trenches. Our simulation shows that the minimum saturation time for conformal atomic layer deposition is proportional to the aspect ratio in the lateral and vertical directions. Due to the effect of gas particles being re-emitted from the bottom of the trench, the minimum surface coverage area is located away from the bottom of the lateral and vertical trench surfaces. The result is similar to those in a paper simulating adsorption inside lateral channels.1

1. J. Ja¨rvilehto et al., Phys. Chem. Chem. Phys., 2023, 25, 22952–22964

The surface termination and interfacial interactions of materials for quantum technologies are critical.Use of atomic layer deposition (ALD) has been explored to provide insight on the chemical environment of the surface while passivating the surface.We explore the nucleation and growth of ALD Al₂O₃ and TiO₂ on diamond surfaces used for quantum sensing.We demonstrate the suppression of dark spins on diamond surface after coalescence of the TiO₂ ALD film on the surface.Additionally, we demonstrate that the nucleation of ALD Al₂O₃ using dimethylaluminum isopropoxide (DMAI) and water is sensitive enough to distinguish between the common surface termination types (H- terminated and O-terminated).We also evaluated methods to pretreat the diamond surface prior to passivating the surface with ALD Al₂O₃. We used in situ spectroscopic ellipsometry measurements to monitor the surface reactions and evaluate the ALD Al₂O₃ nucleation process as a function of different ex situ and in situ surface pretreatments. We found that in situ water dosing and high vacuum annealing provided the most favorable environments for nucleation of ALD Al₂O₃ using DMAI and water ALD. Hydrogen termination passivated both smooth and rough surfaces while triacid cleaning passivated the smooth surface only, with striking effectiveness.

Nuclear fusion holds immense potential to reshape the global energy landscape. To develop mature technologies that can be deployed at power-plant scale, numerous materials-science challenges must be solved. One critical example is the safe, efficient, and loss-free handling of tritium (hydrogen-3), an essential fuel for fusion energy. Tritium permeates many of the materials used in reactor components, leading to structural embrittlement and other hazards associated with the fuel's radioactive properties. Atomic layer deposition (ALD) is emerging as a promising technique for the development of Al₂O₃ permeation barrier coatings that reduce loss of tritium. ALD's ability to produce high-quality, uniform films across complex geometries and components makes it advantageous compared to techniques limited to planar substrates. Though ALD Al₂O₃ coatings are well studied on semiconductor-relevant substrates, the work presented here reports the use of a custom-built ALD system to carry out the first syntheses on fusion-grade reduced-activation-ferritic-martensitic (RAFM) steel.

Prior to deposition, 1 cm × 1 cm RAFM steel substrates were prepared by polishing them to ~15 nm root mean square surface roughness. Al₂O₃ films were then deposited using a thermal ALD process with trimethylaluminum (TMA) and water precursors. Deposition was performed at temperatures between 100–200 °C to determine optimal growth conditions. Once this was achieved, growth rate curves were measured.

The films were characterized using X-ray photoelectron spectroscopy (XPS), X-ray diffraction (XRD), X-ray reflectivity (XRR), and spectroscopic ellipsometry. Our XPS results indicate that the RAFM surface is predominantly iron, in addition to small quantities of chromium oxide. ALD films were primarily stoichiometric Al₂O₃, with some growth conditions resulting in a small aluminum hydroxide component. The XRR and ellipsometry data were used to determine film characteristics such as morphology and ALD film thickness. This required the development of a model in which the film was represented as three layers: a low-density surface oxide, a denser bulk oxide, and an interface oxide in contact with the substrate surface. Growth rate curves and other process development will be presented.

As HARC feature sizes push below 20nm, maintaining stringent critical dimension (CD) control is essential for device performance, reliability, and yield. In advanced etch stacks, post–etch profiles are highly sensitive to incoming mask geometry, with across–wafer bow CD emerging as a dominant systematic variation. Tapered or necked mask profiles exacerbate ion angular scattering and polymer transport imbalance, producing non–uniform sidewall evolution and CD drift. To quantify and mitigate these effects, we employed a physics–based SEMulator3D (SEM3D)^† workflow calibrated via Bayesian optimization to experimental profiles and plasma fundamentals. The calibrated model captured ion–limited etching, neutral–assisted deposition, and polymer redeposition, with the incident ion angular distribution represented by a Voigt profile consistent with pulsed–bias operation.

Tapered, straight, and reverse taper masks revealed a near linear dependence of both bow CD and mask selectivity on mask taper: larger taper increases bow while improving selectivity due to a larger effective opening. A design of experiments (DOE) varying top and bottom CDs confirmed the trade space—bow CD decreases with smaller bottom CD, whereas selectivity improves with larger top CD—exposing a fundamental limitation when taper is left unaddressed. To break this constraint, we introduced a targeted deposition step engineered to reduce taper and drive the mask toward a straighter geometry prior to etch. By tuning the sticking coefficient of depositing neutrals, we modulated within via deposition depth—lower sticking promoted deeper, more conformal coverage—thereby straightening the sidewall and suppressing taper induced aberrations. Simulations showed substantial bow reduction for straightened profiles.

In addition, we investigated cyclical deposition–etch sequencing to manage the dynamic evolution of bow and the risk of top–CD clogging. A dedicated cyclical–process DOE varying sticking coefficient, per–cycle deposition thickness, and cycle count demonstrated that bow growth rate can be actively controlled by tuning deposition parameters and cadence. Low–sticking, moderate–thickness cycles provided the best balance—minimizing bow growth (30–60% retardation observed in simulation) while avoiding opening pinch–off—whereas high–sticking films favored top–side accumulation and premature constriction.

Overall, this study quantifies its impact with a calibrated SEM3D model and demonstrates two complementary mitigation paths: (1) pre–etch deposition to straighten the incoming profile and (2) optimized cyclical deposition–etch to dynamically stabilize sidewalls and suppress bow growth without inducing clogging. Together, these strategies improve across–wafer CD uniformity and expand process window for next–generation HARC nodes.

^†SEMulator3D® is a semiconductor process modeling platform that offers wide ranging technology development capabilities. This product is offered through Lam Research.

Vanadium dioxide (VO₂) is a premier candidate for thermochromic smart windows due to its ability to dynamically modulate solar heat gain. However, achieving high solar modulation (∆T_sol) typically requires a rutile-phase TiO₂ buffer layer to lower the growth temperature of VO₂ [1]. Such buffers are often produced via high-temperature sputtering (>400 °C), limiting the use of temperature-sensitive flexible substrates.

In this work, we demonstrate a low-T ALD route to rutile TiO₂ at process temperatures as low as 220 °C. Utilizing a thermal TDMAT/H₂O process at 200 °C [2,3], we generate "black TiO₂" films. Based on literature [2,3], the characteristic Ti³⁺ defects and oxygen vacancies in these films are believed to bypass the common high-temperature anatase-rutile conversion.

Integrated into VO₂|TiO₂|glass architectures, we achieve ∆T_so > 9% comparable to benchmarks using high-temperature sputtered references (650 °C) [1]. Crucially, this approach removes a major barrier for VO₂ coatings on polymer-based substrates. Preliminary results indicate that this low-T process can be transferred to polyimide (PI), paving the way for flexible VO₂ smart windows.

References

[1] M. Becker et al., ACS Appl. Electron. Mater. 2023, 5, 3560–3570.

[2] J. L. Vazquez‐Arce et al., Adv. Mater. Interfaces 2024, 2400269.

[3] J. Saari et al., J. Phys. Chem. C 2022, 126, 15357–15366.

Low temperature ALD of p-type conducting oxides remains a challenge, particularly as surface chemistry can dominate contact quality and therefore device performance as a function of overall scaling.Furthermore, the surface of p-type oxides is often susceptible to reaction with atmospheric oxygen and water, altering dopant concentrations and affecting process conditions.We have developed a new tin ALD precursor and utilized it for low-temperature, thermal ALD of p-type tin oxides.We have characterized the chemical and physical properties of the precursor, its ALD growth window, and resulting p-type film mobilities.We also have studied the effects of surface treatments on mobility and stability of the resulting films.

In this talk we discuss the results of these studies on p-type tin oxide thin films grown using a novel precursor.This includes QCM measurements under ALD conditions, solution model reactions, and synchrotron studies conducted at the Advanced Photon Source (APS) located at Argonne National Laboratory.The surface reactions of Sn precursors and half-reactions provide insight into the surface of the film and overall manufacturability of p-type oxides in the future.The results of these studies were applied to improved p-type oxide ALD, including doping strategies.Device characterization will also be discussed as time allows.