ALD/ALE 2026 Session AA2-TuM: ALD Dielectric Applications

As silicon scaling approaches its physical limits, indium-based oxide semiconductors have emerged as promising channel materials because they maintain high carrier mobility and drive current even at channel thickness below 5 nm, enabling superior scalability. Among them, In₂O₃ exhibits excellent drive current; however, hydrogen incorporation leads to hydroxyl (OH) formation, resulting in device instability and threshold voltage shifts. Incorporating nitrogen to form indium oxynitride (InON) is expected to enhance mobility while effectively suppressing the formation of hydrogen induced OH bonds, thereby improving device stability.

Despite these advantages, direct deposition of InON via atomic layer deposition (ALD) is challenging because the bonding dissociation energy of In-O (~346 kJ/mol) is significantly stronger than that of In-N (~186 kJ/mol), making it difficult to incorporate sufficient nitrogen during the simultaneous supply of oxygen and nitrogen reactants.^[1,2] In this work, we propose a two-step channel formation strategy: the initial deposition of an indium nitride (InN) thin film followed by an oxidation process to convert it into an InON channel layer.

In this presentation, we report the deposition of sub-5 nm conformal InN films via Hollow-Cathode Plasma (HCP)-enhanced ALD at 240 °C. To improve the structural and electrical stability of the channel, an annealing-based oxidation process was applied, converting InN into the more robust InON and evaluating their integration into top-gated (TG) thin-film transistor (TFT) devices. We investigated the influence of process parameters such as plasma power, process pressure, and deposition temperature for the film characteristics. The 5 nm InON layer was deposited at 240 °C, followed by the deposition of a 5 nm hafnium zirconium oxide (HZO) dielectric layer, and finally a TG-FET was demonstrated using Ni metal contacts. We presented InON TG-FET results, including transfer and output characteristics, temperature dependence, and channel length scaling. Our findings demonstrate that InON-based TFTs with a 100nm channel length achieve an on-current of ~1.2mA/µm at V_D = 1 V, an I_on/I_off ratio exceeding 10⁹, and a contact resistivitywith Ni of 4 x 10^-8Ω·cm². In addition, the △V_th under positive and negative bias stress is 90 and 15 mV, at V_ov = ±1 V.

This work was supported by SK hynix Inc.

[1] Imran, A., et al., Adv. Mater. Interfaces 10, 2200105 (2022).

Dipole technique has been widely investigated to control the threshold voltage (V_th) of metal/High-k CMOS with GAA gate stack in 50 mV increments. La₂O₃ and Al₂O₃ are generally employed as n- and p-type dipoles. However, it remains a big issue of a large V_th shift in the sub-nm region of the dipole layer. In this paper, we investigated flatband voltage (V_fb) shift for SiO₂/dipole/HfZrO₂ stack structure using new LaTiO and AlTiO as n- and p-type dipoles.

p-Si/SiO₂/dipole/HfZrO₂/Au capacitor was fabricated at a maximum process temperature of 400 °C as follows: La₂O₃, TiO₂ and Al₂O₃ dipole layers were deposited on p-Si/SiO₂ (3.6 nm) by ALD at 250 °C with H₂O and La(iPrCp)₃, TDMAT, and TMA, respectively. LaTiO and AlTiO dipoles were also prepared by changing each ALD cycle of La₂O₃ and TiO₂, and Al₂O₃ and TiO₂ by ALD at 250 °C with H₂O, respectively. Next, an HfZrO₂ (2 nm) film was deposited on dipole layer by ALD at 250 °C using TEMA(Hf/Zr)(Hf/Zr = 1/1) cocktail and H₂O. Au gate electrode was deposited on HfZrO₂ film to form capacitor. Finally, forming gas annealing was carried out at 400 °C in 3%H₂.

Dielectric materials, especially insulating polymers, are crucial for various technological applications due to their high breakdown voltage and low cost [1]. However, they generally exhibit low dielectric constant and thermal stability, limiting their use in field as power electronics.

To enhance their dielectric constant, recent studies have explored the elaboration of nanocomposites by adding alumina nanoparticles into a polymer matrix, resulting in significant improvements in dielectric constant and breakdown voltage even at low concentrations [2]. Despite these promising results, the elaboration methods used were incompatible with standard microelectronic processes.

This work studies the elaboration of nanocomposite thin films using microelectronic materials stable up to 400°C, deposited by vacuum deposition techniques. To this end, 100 nm porous SiOCH were deposited by PE-CVD on Si wafers using a porogen approach [3]. Then high-k material was infiltrated into this porous thin film using ALD. The filling process for different materials and precursors was characterized using physicochemical methods (XRF, ellipsometry, XRR, ToF-SIMS, FTIR, TEM). Then, the electrical properties were studied (dielectric constant, dielectric losses, breakdown voltage). In the case of trimethylaluminum/O₃, the results highlight that the filling of the nanometric pores of the porous SiOCH occurs in the first ALD cycles (<5). Using an optimized recipe, a maximum filling of ≈50% of the porosity was obtained. As the number of cycles increases, high-k growth continues on the surface at a rate similar to that observed on Si. FTIR analysis reveals the formation of -OH groups in the first cycles, which increases dielectric constant and dielectric losses. A similar behavior is observed when using H₂O as oxidant. However, after 25 ALD cycles, the disappearance of -OH groups is observed for the TMA/O₃ process. One hypothesis is that the alumina layer formed on top of the porous structure becomes thick enough to limit H₂O adsorption into the matrix. This leads to the elaboration of composites with a dielectric constant 42% higher than that of the porous matrix while maintaining low dielectric losses. Finally, infiltration of porous SiOCH with HfO₂ and HfZrO₂ (from chlorinated precursors and water), which have higher dielectric constant than Al₂O₃, also enables enhanced dielectric properties without the presence of -OH groups. But in this case the filling rate is slightly lower than that observed with alumina.

In conclusion, this work demonstrates an easy approach for the elaboration of nanocomposites using standard microelectronic materials to achieve a broader range of electrical properties.

[1] Thakur, Y. et al.; Nanoscale 2017, 9 (31), 10992–10997.

[2] Zhang, T. et al.; Sci. Adv. 2020, 6 (4), eaax6622.

[3] Grill, A. et al.; Appl. Phys. Lett. 2001, 79 (6), 803–805.

Transport and breakdown field characteristics of GaN-based HEMT technologies are limited by high and non-uniform peak electric fields at the drain-edge of the gate. The non-uniform peak field causes premature electric field induced breakdown limiting the device performance [1]. These deleterious effects can be mitigated by integrating films with high dielectric constants (high-k, >20), such as TiO₂ [2-4]. For HEMTs, increased k leads to increased power handling capability without significant reduction in operation frequency. Thus, the goal is to integrate the highest k material possible. ALD provides flexibility in device design, integration and back-end-of line compatibility, making it a promising route for these high-k films. However, ALD high-k dielectrics with ideal interfaces and reduced trapping on AlGaN/GaN HEMTs have not been reported. In this talk, we report on the optimization and electrical characterization of the ALD TiO₂ interface with AlGaN-barrier HEMT structures.

Previously optimized deposition parameters [3] served as the baseline to further optimize electrical performance by pretreating the dielectric-barrier interface of Al_0.25Ga_0.75N/GaN HEMT structures. Ex-situ pretreatments including NH₄OH, UV O₃+BOE, piranha and O₂ plasma descum were studied. Similarly, in-situ UHV annealing, plasma treatments and their combinations were also studied. The optimum interface was found to be a combination of ex-situ O₂-plasma descum and in-situ H₂ and N₂ plasma treatments. Initial results using this preparation, a 20nm TiO₂ film demonstrated a reduction in gate leakage by 10⁵ compared to a Schottky gate,zero CV hysteresis, a dielectric constant ≥ 50, and no significant change in 2DEG density. Even though the ALD TiO₂ has a narrower bandgap than AlGaN-barrier material, its large dielectric constant provides a pathway forward for dielectric permittivity engineering within the device structure. This engineering approach can improve breakdown voltage, lowers gate leakage and minimizes non-ideality over the state-of-the-art.

References:

1. Turuvekere et al., IEEE Trans. Electr. Dev. 60, 3157 (2013).
2. Rahman et al., Appl. Phys. Lett. 119, 193501 (2021).
3. Nepal et al., APL Electr. Dev. 1, 036102-1 (2025).