IWGO 2026 Session IWGO-FrM1: Plenary Session III

Benefiting from advances in large-diameter Ga₂O₃ wafers and processing technologies, Ga₂O₃ power device technology has made rapid progress in recent years. Reports of large-area, ampere-class Ga₂O₃ power devices have emerged worldwide, extending beyond fundamental research demonstrations to device packaging, circuit-level testing, and ruggedness evaluations. These milestones have established Ga₂O₃ as the only ultra-wide-bandgap (UWBG) semiconductor that has reached such critical steps toward practical commercialization and application.

This talk will introduce our recent progress on exploring Ga₂O₃ devices towards high-voltage, high-temperature, and high-power applications, addressing their critical barriers towards applications, and highlighting their potential to expand the frontier of power electronics.

Multidimensional device architectures—such as superjunction, FinFET, and multi-channel—can break the performance limit of 1D power devices and enable device performance improvements through geometrical scaling. To address the limitations in p-type doping in Ga₂O₃, we developed heterogeneous superjunctions based on charge-balanced NiO/Ga₂O₃ architectures. After the first demonstration of 2 kV Ga₂O₃ vertical superjunction devices [IEDM 23], we have demonstrated lateral NiO/Ga₂O₃ architectures superjunction diodes and transistors achieving breakdown voltages exceeding 10 kV and stable operation up to 250 °C [EDL 23, IEDM 24].

In parallel, scaling up current and power require advanced thermal management, particularly given the low thermal conductivity of Ga₂O₃. We explored the path of addressing the thermal challenge of Ga₂O₃ through packaging. We employed the junction-side cooling package to directly extract heat from the active junction and demonstrate a thermal resistance comparable to commercial SiC devices [T-PEL 21, EDL 22]. We then developed novel device-package interface designs for electrical-thermo-mechanical co-optimization, demonstrating the first ultra-wide bandgap power module capable of 1000 V, 200 A switching [IEDM 25]. Most recently, we upscale the power capacity of this module to megawatt and demonstrate its advantageous performance in pulsed power electronics applications [Nat. Commun. 26].

Reliability and robustness are also critical to power device applications. Despite the lack of effective p-type doping, we demonstrate the avalanche and surge robustness in NiO/Ga₂O₃ heterojunctions [Nat. Commun. 24], as well as good bipolar stability in this heterojunction [APL 25]. Overall, coordinated progress in device, packaging, and reliability is paving the way for deployment of Ga₂O₃ in next-generation power electronics.

The metal–oxide–semiconductor (MOS) structure is a fundamental component in electronic devices. Among various insulators, SiO₂ is regarded as the most suitable material for Ga₂O₃–based electronics owing to its sufficiently wide bandgap, excellent insulating properties, and high thermal stability. For MOSFET operation, electrical defects at the insulator/semiconductor interface not only act as scattering centers in the MOS channel but also play a critical role in determining reliability factors such as threshold–voltage stability. Therefore, improving the MOS interface quality remains an important research challenge. However, only a limited number of studies have reported on SiO₂/Ga₂O₃ MOS structures [1], and research and development in this area is still in its early stages.

The fabrication of Ga₂O₃–based MOS devices inevitably involves the deposition of insulating films, for which post–deposition annealing (PDA) in an oxygen atmosphere is widely employed to improve film quality. In our study, SiO₂ films were directly deposited on wet–cleaned β–Ga₂O₃(001) substrates by plasma–enhanced chemical vapor deposition. We first investigated the impact of PDA on the electrical properties of SiO₂/β–Ga₂O₃ MOS capacitors [2]. Although high–temperature PDA in O₂ ambient effectively reduced electrical defects at the interface, it also caused a decrease in the net donor density in Ga₂O₃, suggesting the formation of deep acceptor–type defects, likely associated with oxygen interstitials or gallium vacancies. However, subsequent annealing in N₂ ambient restored the donor density to its initial value. As a result, the combined O₂ and N₂ annealing process yielded a low interface–state density (D_it) of approximately 10¹¹ cm⁻²eV⁻¹ near the conduction–band edge of Ga₂O₃. We also confirmed enhanced immunity to gate–bias stress, indicating improved long–term MOSFET reliability. Furthermore, we demonstrated the significant benefits of post–metallization forming–gas annealing (FG–PMA) for SiO₂/β–Ga₂O₃ MOS structures [3]. FG–PMA at relatively low temperatures below 400 °C effectively reduced both D_it and near–interface traps, leading to further improvements in device performance and long–term reliability. When FG–PMA was performed following the combined O₂ and N₂ annealing, an extremely low D_it in the low–10¹⁰ cm⁻²eV⁻¹ range was achieved through hydrogen passivation of electrical defects in the SiO₂/β–Ga₂O₃ MOS system.

This work was partly based on results obtained from a project, JPNP22007, commissioned by NEDO.

[1]K. Kita et al., ECS Trans. 92, 59 (2019).

[2] T. Kobayashi et al., Appl. Phys. Lett. 126, 012108 (2025).

This work analyzes Ga₂O₃ Schottky Barrier Diodes (SBDs) as half-wave AC rectifiers for a 473 V_RMS (669 V_peak) sine wave (Fig. 1). Fundamentally, transmitting power through higher voltage allows for lower currents, which improves system-level efficiency by reducing Joule heating and the requisite conductor weight [1]. We evaluate Ga₂O₃ diodes as AC rectifiers, a basic power-handling function, in voltage-dominated power transfer at voltages approaching the standard 480 V_RMS used for heavy industry in the USA.

The Ga₂O₃ devices in this analysis are packaged prototypes fabricated by Novel Crystal Technologies (NCT). They are compared to SiC devices fabricated by GeneSiC. Both devices use a TO-247 package. Table 1 contains measured diode characteristics. For half-wave rectifier testing, the diode is placed in series with an AC power supply and a variable resistor (the load). The power supply is set to source a 480 V_RMS, 1 kHz sine wave. An oscilloscope is used to measure V_in, V_load, and I_load. A sine or piece-wise function is fit to the measured data using SciPy for analysis. The efficiency of the diode is analyzed by comparing the on-state input power to the on-state output power minus the off-state output power. Thus, an ideal diode with no leakage or on resistance would be 100% efficient.

β-Ga₂O₃ power diodes havethe potential in applicationsat high-temperature and high-voltage environments. The NiO based junction termination extension (JTE) can prevent the diodes’ premature breakdown, fully leveraging the high E_C of β-Ga₂O₃. However, the reliability of β-Ga₂O₃Schottky barrier diode (SBD) featuring JTE under high-temperature storage stress (HTSS) warrants attention. In this study, a HTSS test at 250 ℃ was conducted on JTE-SBD and the changes in device performance over the storage time were investigated. During the test, the turn-on voltage (V_on) of diodes increased from 0.90 V to 1.10 V, while the breakdown voltage (BV) showed a phenomenon of first increasing and then decreasing. The C-V measurements shows that the carrier concentration (N_A) of NiO initially decreases and subsequently increases, leading to the variations of the peak electric field. To enhance the device reliability, a 300 ℃-10 mins oxygen annealing process has been proposed. By this approach, the V_on of JTE-SBD only increased 0.10 V during the test. Due to the lower and more stable N_A of NiO, the average BV of the annealed JTE-SBD maintained 2231 V even after 124 hours HTSS. Finally, XPS spectra illustrates the reasons for the changes of N_A of NiO. This study enhances the understanding of the reliability of β-Ga₂O₃ and NiO, providing effective strategy for improving the stability of NiO/β-Ga₂O₃ JTE-SBD.

We report on the creation of >1 GW/cm² NiO_x field-plated heterojunction diodes (FP-HJDs) on MOCVD-grown (110) and (010) drift layers achieving breakdown voltages of up to 7.58 kV and parallel-plane critical electric fields (E_||) of up to 4.14 MV/cm. MOCVD epilayers were grown on conductive Sn-doped β-Ga₂O₃ (010) and (110) substrates using TMGa, O₂, Ar carrier gas, and SiH₄ as the silicon dopant source. Intentionally Si doped 40 μm and 6.2 μm epitaxial films were grown on the (110) and (010) substrates respectively. The 40 μm film was CMP polished for 1 hr. which smoothed the surface and reduced the epilayer thickness to ~25 μm. The sample surface exhibited global variation in height, but locally smooth surfaces for devices. The anode for the circular field-plated HJDs was created by depositing a stack of 27 nm p^- NiO_x, 20 nm p⁺ NiO_x, and Ni/Au/Ni metal. Next, a 2 μm deep self-aligned etch was performed via a BCl₃ ICP process to isolate the p-n junction. Finally, a 1 μm thick SiO₂ FP dielectric, Ni/Au FP metal, and a Ti/Au backside Ohmic contact were deposited. High voltage C-V showed a flat N_D-N_A concentration of 2.5 × 10¹⁶ cm^-3 and 5 × 10¹⁵ cm^-3 for the (010) and (110) epilayers respectively. J-V measurements on the 6.2 μm (010) epi resulted in J = 700 A/cm² at 4 V, HJD ideality factors of 1.29, V_bi of 2 V, rectification ratio of 10¹¹, and a differential specific on resistance (R_On,sp) value of 2.36 mΩ.cm². Breakdown on the (010) epi was 1.64 kV, leading to a E_||of 4.02 MV/cm and a PFOM of 1.14 GW/cm². J-V on the ~25 μm (110) epi resulted in J = 100 A/cm² at 5.6 V, HJD ideality factors of 1.08, V_bi of 1.8 V, rectification ratio of 10¹⁰, and a R_On,sp value of 32.2 mΩ.cm². Breakdown on the (110) epi was 7.58 kV, leading to a E_||of 4.14 MV/cm and a PFOM of 1.78 GW/cm². HJD results on the (010) and (110) epilayers are state-of-the-art, with E_|| and PFOM values rivalling those achieved on commercial HVPE (001) epilayers. Additionally, this is the first demonstration of devices on (110) epilayers, with the (110) results showing high promise for the material orientation.